VHDL—双边沿触发加法计数器与七段数码管显示

使用拨位开关作为手动时钟，实现双边沿触发加法计数器，将上升沿与下降沿分别加法计数。该项目工程主要由：顶层文件、分频元件、加法计数器和数码管显示元件组成。

1）顶层文件：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity led_sm is    
    port
    (   
        inclk: IN STD_LOGIC;
        reset: IN STD_LOGIC;
        key: IN STD_LOGIC;
        data_hex7:out std_logic_vector(7 downto 0);--数码管段码输出
        com:out std_logic_vector(3 downto 0)--位码输出      
    );
end led_sm;

architecture Lin of led_sm is

    component gen_div is--分频元件调用声明
    generic(div_param:integer:=2);--默认是4分频
    port
    (
        clk:in std_logic;
        bclk:out std_logic;
        resetb:in std_logic
    );
    end component;

    component DECL7S is
    port
    (
        cnt_clk: IN STD_LOGIC;
        resetin: IN std_logic;
        data_in1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        data_in2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        com : out std_logic_vector(3 downto 0) -- 选通引脚
    );
    end component DECL7S;

    component CNT4 IS
    PORT(
        CLK:IN STD_LOGIC;
        Q_out1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        Q_out2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
        );
    END component CNT4;


    signal data_num1:std_logic_vector(3 downto 0);
    signal data_num2:std_logic_vector(3 downto 0);
    --Converted data
    signal data_sm:std_logic_vector(7 downto 0);
    signal key_in :std_logic;
    signal inkey :std_logic;

BEGIN

gen_key:
    gen_div generic map(200000) --10ms延时消抖
    port map--分频元件例化
        (
            clk=>inclk,
            resetb=>not reset,
            bclk=>key_in
        );

gen_cnt_key: --拨码开关延时消抖
    process(key_in,key)
    begin
    if key='1' then
        if rising_edge(key_in) then --延时消抖
            if key='1' then inkey<=key;
            else inkey<='0';
            end if;
        end if;
        else inkey<='0';
    end if;
    end process;    

part1:
    CNT4 port map
    (
        CLK =>inkey, 
        Q_out1=> data_num1,
        Q_out2=> data_num2
    );


part2:  --the led-change process
    DECL7S port map
    (
        cnt_clk => inclk,
        resetin => reset,
        data_in1 => data_num1,
        data_in2 => data_num2,
        LED7S =>data_sm,
        com =>com
    );  

    data_hex7<=data_sm; 

END Lin;

2）分频元件：

--通用偶数分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  gen_div is
    generic(div_param:integer:=1);
    --分频因子,分频为2*div_param，默认2分频
    port
    (
        clk:in std_logic;--输入时钟
        bclk:out std_logic;--分频输出
        resetb:in std_logic--复位信号
    );
end gen_div;

architecture behave of gen_div is
signal tmp:std_logic;--输出暂存寄存器
signal cnt:integer range 0 to div_param:=0;--计数寄存器
begin
------------------------------
    process(clk,resetb)
    begin
        if resetb='1' then --reset有效时,bclk始终是0
            cnt<=0;
            tmp<='0';
        elsif rising_edge(clk) then
            cnt<=cnt+1;
            if cnt=div_param-1 then
                tmp<=not tmp;--取反信号
                cnt<=0;
            end if;
        end if;
    end process;
    bclk<=tmp;--输出
--------------------------------
end behave;

3）加法计数器：

LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 ENTITY CNT4 IS
 PORT(CLK:IN STD_LOGIC;
        Q_out1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        Q_out2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
        );
 END;

 ARCHITECTURE bhv OF CNT4 IS
begin
------------------------------
      PROCESS(CLK) 

    variable Q1: STD_LOGIC_VECTOR(3 DOWNTO 0);
    variable Q2: STD_LOGIC_VECTOR(3 DOWNTO 0);
    variable Q_out:STD_LOGIC_VECTOR(3 DOWNTO 0);
-----变量的赋值 
      BEGIN
      if rising_edge(CLK) THEN 
          Q1 :=Q1+1;
          elsif falling_edge(CLK) THEN 
          Q2 :=Q2+1;
      end if;
      Q_out:=Q1+Q2;

      if Q_out>9 
        then Q_out2<="0001";Q_out1<=Q_out-10;
        else Q_out2<="0000";Q_out1<=Q_out;
      end if;

      END PROCESS;
END bhv;

4）数码管显示元件：

LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 ENTITY DECL7S IS
    PORT (
        cnt_clk: IN std_logic;
        resetin: IN std_logic;
        data_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        data_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        com : out std_logic_vector(3 downto 0) -- 选通引脚
        );
    END ;

architecture Lin of DECL7S is   

    component gen_div is--分频元件调用声明
    generic(div_param:integer:=2);--默认是4分频
    port
    (
        clk:in std_logic;
        bclk:out std_logic;
        resetb:in std_logic
    );
    end component;

signal clk_sm:std_logic;--50k时钟，T=20us
signal cnt_50k:std_logic_vector(1 downto 0);--对clk_sm计数，产生4种状态
signal data_in :STD_LOGIC_VECTOR(3 DOWNTO 0);




BEGIN   
gen_100k: --分频产生50k脉冲
        gen_div generic map(400)--800分频的,产生50k脉冲
        port map--分频元件例化
        (
            clk=>cnt_clk,
            resetb=>not resetin,
            bclk=>clk_sm
        );


gen_cnt_50k:--cnt_50k循环计数,四个状态的循环周期是20us*4=80us，即为扫描周期
    process(clk_sm)
    begin
        if rising_edge(clk_sm) then
            cnt_50k<=cnt_50k+'1';
        end if;
    end process;

    process(cnt_50k)
    begin
        case cnt_50k is--循环扫描
            when "10"=> com<="1101";data_in <=data_in1;--十位
            when "11"=> com<="1110";data_in <=data_in2;--个位
            when others=> com<="1111";--全灭
        end case;       
    end process;

    process(data_in)    
    begin

    CASE data_in IS 
        WHEN "0000" => LED7S <= X"03";
        WHEN "0001" => LED7S <= X"9F";
        WHEN "0010" => LED7S <= X"25";
        WHEN "0011" => LED7S <= X"0d";
        WHEN "0100" => LED7S <= X"99";
        WHEN "0101" => LED7S <= X"49";
        WHEN "0110" => LED7S <= X"41";
        WHEN "0111" => LED7S <= X"1F";
        WHEN "1000" => LED7S <= X"01";
        WHEN "1001" => LED7S <= X"09";
        when others=>LED7S<=X"FF";--支持0-9字符
        END CASE ;  

    END process;
END Lin;