VHDL—基于拨位开关的音符发声

 理解蜂鸣器奏乐的实现原理，将三个拨位开关所代表的0~7，然后将拨位开关所代表的结果作为音频输出的选择条件；实现程序主要由：顶层文件、分频元件、蜂鸣器元件构成。

顶层文件：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is
    port
    (
        clk_in:in std_logic;--时钟
        reset_in :in std_logic;
        keyin:in std_logic_vector(2 downto 0);
        outbell:out std_logic--bell脉冲输出
    );
end entity;

architecture lin of top is
signal bells:std_logic;
signal clk_tmp:std_logic;--10M脉冲
signal clk_tmp2:std_logic;--10M脉?
signal key_in:std_logic_vector(2 downto 0);
signal pre_div:std_logic_vector(15 downto 0);
---------------------------
    component gen_div is--分频元件调用声明
    generic(div_param:integer:=2);--4分频的,产生10M脉冲
    port
    (
        clk:in std_logic;
        bclk:out std_logic;
        resetb:in std_logic
    );
    end component;

    component bell is
    port
    (
        clkin:in std_logic;--时钟
        resetin :in std_logic;
        key:in std_logic_vector(2 downto 0);
        bell_out:out std_logic--bell脉冲输出
    );
    end component;

 begin
outbell <=bells;
key_in <=keyin;     

gen_10M: --分频产生10M脉冲
        gen_div generic map(2)--4分频的,产生10M脉冲
        port map--分频元件例化
        (
            clk=>clk_in,
            resetb=>not reset_in,
            bclk=>clk_tmp
        );

bell8s:
         bell port map
         (
            clkin=>clk_tmp,
            resetin =>reset_in,
            key=>key_in,
            bell_out=>bells
         );

end lin;    

分频元件：

--通用偶数分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  gen_div is
    generic(div_param:integer:=1);
    --分频因子,分频为2*div_param，默认2分频
    port
    (
        clk:in std_logic;--输入时钟
        bclk:out std_logic;--分频输出
        resetb:in std_logic--复位信号
    );
end gen_div;

architecture behave of gen_div is
signal tmp:std_logic;--输出暂存寄存器
signal cnt:integer range 0 to div_param:=0;--计数寄存器

begin
------------------------------
    process(clk,resetb)
    begin
        if resetb='1' then --reset有效时,bclk始终是0
            cnt<=0;
            tmp<='0';
        elsif rising_edge(clk) then
            cnt<=cnt+1;
            if cnt=div_param-1 then
                tmp<=not tmp;--取反信号
                cnt<=0;
            end if;
        end if;
    end process;
    bclk<=tmp;--输出
--------------------------------
end behave;

蜂鸣器元件：

--蜂鸣器,发出1,2,3,4,5,6,7音
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bell is

    port
    (
        clkin:in std_logic;--时钟
        resetin :in std_logic;
        key:in std_logic_vector(2 downto 0);
        bell_out:out std_logic--bell脉冲输出
    );
end entity;

architecture behave of bell is
------------------------------
signal bell_tmp:std_logic;
signal pre_div:std_logic_vector(15 downto 0);--分频系数
---------------------------
begin
-------------------
bell_out<=bell_tmp;
----------------------
    process(clkin,key,resetin)
    variable cnt:std_logic_vector(15 downto 0):=X"0000";    
    begin
        if resetin='0' then
            bell_tmp<='0';--复位时，bell不出声
            cnt:=X"0000";
            pre_div<=X"4A8B";--1
        else
            if rising_edge(clkin) then
                if cnt>=pre_div then   --  > & =
                    bell_tmp<=not bell_tmp;
                    cnt:=X"0000";                   
                    if key="000" then
                        pre_div<=X"0000";--2
                    elsif key="001" then
                        pre_div<=X"426E";--2
                    elsif key="010" then
                        pre_div<=X"3B2F";--3
                    elsif key="011"then
                        pre_div<=X"37F6";--4
                    elsif key="100" then
                        pre_div<=X"31D3";--5
                    elsif key="101"then
                        pre_div<=X"2C63";--6
                    elsif key="110" then
                        pre_div<=X"2789";--7
                    elsif key="111" then
                        pre_div<=X"4A8B";--1
                    end if;
                else
                    cnt:=cnt+'1';
                end if;
            end if;
        end if;
    end process;
----------------------------------------------------------

end behave;