VHDL—基于分频器的加法计数器与LED显示

将加法计数器的结果作为3个led的输出，并通过修改分频参数更改闪烁时长。

该程序设计分为三部分，分别是：顶层元件调用程序、通用偶数分频器、加法计数器。

1）通用偶数分频器

--通用偶数分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  gen_div is
	generic(div_param:integer:=1);
	--分频因子,分频为2*div_param，默认2分频
	port
	(
		clk:in std_logic;--输入时钟
		bclk:out std_logic;--分频输出
		resetb:in std_logic--复位信号
	);
end gen_div;

architecture behave of gen_div is
signal tmp:std_logic;--输出暂存寄存器
signal cnt:integer range 0 to div_param:=0;--计数寄存器
begin
------------------------------
	process(clk,resetb)
	begin
		if resetb='1' then --reset有效时,bclk始终是0
			cnt<=0;
			tmp<='0';
		elsif rising_edge(clk) then
			cnt<=cnt+1;
			if cnt=div_param-1 then
				tmp<=not tmp;--取反信号
				cnt<=0;
			end if;
		end if;
	end process;
	bclk<=tmp;--输出
--------------------------------
end behave;

2）顶层调用文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity led_adder is 
	port
	(
	    inCLK,RST_in,EN_in,LOAD_in: IN STD_LOGIC;
		LED:out std_logic_vector(2 downto 0)--led输出
	);
end entity;

architecture Lin of led_adder is
	
---------------------------------
signal clk_tmp:std_logic;--半秒脉冲

	component gen_div is--分频元件调用声明
	generic(div_param:integer:=40000000);--20000000分频的,产生半秒脉冲
	port
	(
		clk_in:in std_logic;
		bclk:out std_logic;
		resetb:in std_logic
	);
	end component gen_div;
---------------------------------
	component CNT10 is	
	PORT 
	(
		CLK,RST,EN,LOAD:IN STD_LOGIC;  --
		DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
	end component CNT10;
	signal num:STD_LOGIC_VECTOR(3 DOWNTO 0);
	signal data_in:std_logic_vector(3 downto 0);
---------------------------------------
begin

gen_1s: 
	gen_div port map
	(
		CLK_in=>inCLK,
		resetb=>not RST_in,
		bclk=>clk_tmp
	);
---------------------------------------
part1:  --CNT10 process
	CNT10 port map
	(
		CLK =>clk_tmp,RST =>RST_in, EN =>EN_in, LOAD =>LOAD_in, -- 
		DOUT => num
	);

	data_in <= num;
---------------------------------------

	process(data_in) BEGIN
	CASE data_in IS 
		WHEN "0000" => LED <= "000";
		WHEN "0001" => LED <= "001";
		WHEN "0010" => LED <= "010";
		WHEN "0011" => LED <= "011";
		WHEN "0100" => LED <= "100";
		WHEN "0101" => LED <= "101";
		WHEN "0110" => LED <= "110";
		WHEN "0111" => LED <= "111";
		when others=>  LED <= "000";
		
		END CASE ;
	end process;
----------------------------------------------------------
	
end Lin;

3）加法计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--v1.0 使用拨码开关产生时钟信号，不稳定。
--v1.1 增加分频器，以此产生时钟信号

ENTITY CNT10 IS
	PORT (CLK,RST,EN,LOAD:IN STD_LOGIC;  --
		DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
		  );
	END CNT10;

ARCHITECTURE behav OF CNT10 IS
------------------------------
	BEGIN 
		 
		PROCESS (CLK,RST,EN,LOAD)
		VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN 
		IF RST='0' THEN Q:=(OTHERS=>'0'); 
		ELSIF RISING_EDGE(CLK) THEN  --FALLING_EDGE(CLK)   CLK'EVENT AND   CLK ='0' 改为下降沿触发
		IF EN='1' THEN 
		ELSE
			IF Q<7 THEN Q:=Q+1;   --the biggest number is 7
				ELSE Q := (OTHERS =>'0');
			END IF;
		END IF;
		END IF;

			DOUT <=Q;
		END PROCESS;

	END behav;

程序实现效果图